As is known in the prior art, in order to provide a fast response to large changes in load current and input supply voltage, the most frequently used form of step down or buck switching regulator employs constant frequency peak current control. An example of such a prior art switching regulator is illustrated in FIG. 1(a). FIG. 1(b) contains timing diagrams illustrating discontinuous current mode and continuous current mode operation of the prior art switching regulator of FIG. 1(a).
Referring to FIG. 1(a), the switching regulator includes an input voltage source 101 having a first lead coupled to a first lead of a switch, SW 103; a current measurement unit 102; a diode 137 having a cathode coupled to a second lead of the switch 103; an inductor 105 having a first lead coupled to the second lead of the switch 103; a capacitor 106 having a first lead coupled to a second lead of the inductor 105; a pair of resistors R1, R2, 111, 110 coupled in series with one another and coupled in parallel with the capacitor 106, a load 112 coupled in parallel with the capacitor 106, and a control circuit 200, which functions to control the overall operation of the switching regulator. As shown in FIG. 1(a), second leads of each of the voltage source 101, the diode 137 (i.e., the anode), the capacitor 106, the series resistors 110, 111 and the load 112, are coupled to ground.
The control circuit 200 includes an error amplifier 114 which receives a reference voltage in its non-inverting input; a loop filter 115 which receives the output of the error amplifier 114; a summing unit 118 which receives the output from the loop filter 115 as one input and the output of the current measurement unit 102 as a second input; a comparator 119 which receives the output of the summing unit 118 as an input; a clock generator 121; and a latch 123 (e.g., an SR flip-flop), which receives both the output of the clock 121 and the output of the comparator 119, as input signals. As also shown in FIG. 1(a), the output of the latch 123 functions as a control signal for controlling the opening and closing of switch 103, and a portion of the voltage across load 112 is fed back to the inverting input of the error amplifier 114 of the control circuit 200. The operation of the switching regulator illustrated in FIG. 1(a) will now be described.
Referring again to FIGS. 1(a) and 1(b), during operation a fraction of the regulated output voltage, across load 112, is determined by resistors R2 110 and R1 111, and this voltage is coupled to the negative terminal or inverting input of the error amplifier 114 via lead 109. A set point or reference voltage 113, which is determined based on the desired load voltage, is provided to the positive terminal or non-inverting input of the error amplifier 114. The output of the error amplifier represents the difference between the desired and measured value of the output voltage 108. The output of the error amplifier is coupled to the loop filter 115, which functions to provide frequency compensation for the control loop to insure suitable transient response and steady state accuracy.
Clock 121 produces pulses at a repetition period TCLOCK, which is used to set the S-R latch 123 via the set input, S, causing the Q-output of S-R latch 123 to turn ON switch SW 103 through lead 124. While switch SW 103 remains ON, the current through inductor 105 gradually increases. The increasing value of inductor current IL 104 is converted to a proportional voltage by switch current measurement unit 102, and the converted voltage is then applied to the input 131 of summing unit 118 via lead 117. The output 132 of summing unit 118, which indicates the voltage difference between the output 116 of loop filter 115 and the measured increasing inductor current IL 104, is converted to a logic level by comparator 119. The output of comparator 119 is then applied to the reset input of S-R latch 123. When the S-R latch 123 is reset by the output of comparator 119 signal at input 135, switch SW 103 turns OFF. It is noted that this occurs when the inductor current IL 104 reaches a positive value set by the output of the loop filter 115.
When the switch SW 103 is turned OFF, inductor current IL 104 flows through the diode 137 until it reaches zero, and remains zero until the next clock pulse is generated by clock 121 if the load current ILoad is small. As shown in FIG. 1(b), immediately after switch-ON time TON expires (i.e. TON=0), inductor current IL 104 declines to zero until switch SW 103 is turned ON again. If the load current ILOAD 107 is assumed small, inductor current IL 104 remains zero until the next clock pulse or cycle. Alternatively, if the load current ILOAD 107 is large, the value of inductor current IL 104 reaches IVALLEY at the next clock pulse (i.e., the load current does not go to zero), as shown in FIG. 1(b). Capacitor 106 smoothes and averages the inductor current IL 104 to produce load current ILOAD 107.
In the case where the inductor current IL 104 is zero for some period of the cycle, the mode of operation is referred to as discontinuous current mode or DCM, while the case where the inductor current IL 104 is greater than zero for the entire duration of the cycle is referred to as continuous current mode or CCM.
While the foregoing circuitry is operable as a switching regulator, it is inadequate for use in many applications including, for example, portable battery powered devices (e.g., cell phones). As is known, in order to maximize run time on battery charge, regulators for these devices must provide very high efficiency under conditions of widely varying load and input voltages. The prior art technique described above and illustrated in FIG. 1(a) is inadequate because it suffers from significant losses due to a forward voltage drop in the diode 137.
Attempted prior art solutions for this problem have been focused on replacing the diode with a low side MOS transistor switch for much smaller “ON” voltage drop. Nonetheless, this approach requires significant changes to the controller in order to generate the proper gate drive signal for the MOS transistor switch.
In continuous current mode, the gate drive signal for the low side switch is normally the inversion of the drive signal for the main switch. In contrast, discontinuous current mode requires the low side switch to be turned OFF at the time when the inductor current falls to zero to prevent reverse current flow and large power losses. Furthermore, the operation of the low side switch and the main switch must be non-overlapping or must not be simultaneous cross-conducting. If both switches are ON at the same moment for even a short period of time, a large shoot-through current flows from the input voltage VIN to ground GND, which can dramatically impair the efficiency of the circuit and even possibly damage the switches due to overheating. Conversely, if both switches are turned OFF simultaneously, “dead time” or a non-conducting period is generated, causing the inductor current to flow through the body diodes of the switches and resulting in power losses due to the large forward voltage drop of the diodes.
One method of correcting the foregoing problem is by incorporating an adaptive dead time gate drive controller. Detailed discussions of this solution can be found, for example, in U.S. Pat. No. 6,396,250, titled “CONTROL METHOD TO REDUCE BODY DIODE CONDUCTION AND REVERSE RECOVERY LOSSES.” In brief, the disclosed device senses the voltage of the terminal between the high-side switch and the low-side switch to provide an indication of pulse delay period for activating the high-side switch or the low-side switch. A learning circuit is used to set the time delays to a minimum value to avoid shoot-through current. Thus, by minimizing the non-overlap times where the body diode of a synchronous rectifier conducts, power losses are reduced. However, this prior art is defective in that the additional components associated with this learning circuit increase cost and design complexity to the point where the design is no longer a practical solution for many applications.
Another disadvantage of the conventional method, as illustrated in the regulator of FIG. 1(a), results from the additional reduction in efficiency caused by switching losses in the gate drives for the MOS switches. These losses are especially significant at low load currents because the switching losses occur at every transition of the clock, even though the small load currents could easily be supplied from the charge stored in capacitor 106 for relatively long periods of time without appreciable change in output voltage 108, for example, by switching much less frequently.
To remedy this problem, it has been proposed that the controller for controlling the switching regulator be operated in bursts separated by periods of “sleep time” when all the power switches and portions of the controller are turned OFF. This method minimizes the switching losses at small load currents. Detailed discussions of this prior art technique can be found in U.S. Pat. No. 6,304,066, titled “CONTROL CIRCUIT AND METHOD FOR MAINTAINING HIGH EFFICIENCY OVER BROAD CURRENT RANGES IN A SWITCHING REGULAR CIRCUIT,” and U.S. Pat. No. 6,307,356, titled “VOLTAGE MODE FEEDBACK BURST MODE CIRCUIT.” Nonetheless, one shortcoming of this method is that it requires extensive additions to the controller of the switching regulator, further complicating the circuit. Such switching regulators are also not maximally effective from an efficiency viewpoint since it still allows multiple switching cycles during the burst.
Another shortcoming of the fixed frequency current mode switching regulator shown in FIG. 1(a) results from an inherent stability problem when the duty cycle for switching TON to TCLOCK exceeds 50% (i.e. when the switch is ON for more than 50% of any given switching cycle). Since controlling the duty cycle of switch SW 103 regulates the load voltage 108, when the duty cycle for TON to TCLOCK exceeds 50%, switch SW 103 causes the load voltage and therefore the switching regulator 100 to become unstable. This phenomenon is of concern because it prevents the switching regulator's full current supply capabilities to be carried out at higher duty cycles. To maintain stability of the current mode switching regulator, the current-derived signal used in the controller for controlling the switching regulator can be adjusted by supplying a slope compensation signal. However, at large duty cycle, slope compensation in turn causes a reduction in load current and power efficiency of the switching regulator.
U.S. Pat. No. 6,498,466, titled “CANCELLATION OF SLOPE COMPENSATION EFFECT ON CURRENT LIMIT,” recommends a solution to this dilemma by providing a control circuit for the current mode switching voltage regulator that can adjust its switching threshold with respect to the magnitude of a slope compensation signal so that a substantially constant maximum current limit of the regulator may be maintained at greater duty cycles. The drawback of this method is that the implementation of such a control circuit adds a significant amount of electrical components to the switching regulator, resulting in increased size, cost and design complexity to the controller.